A host computer system, including an addressable main memory storing data pages
and a page table, emulates a target computer system which includes an emulated
target central processing unit, an emulated target associative memory and an emulated
target multi-digit incrementable validity counter. The target associative memory
stores a plurality of entries in accordance with a low order virtual address component
issued by the target processor when access to a given page in main memory is sought.
Each entry in the target associative memory includes fields respectively holding:
1) a high order virtual address component; 2) a real page address; and 3) a multi-digit
validity count. The target multi-digit counter stores a current validity count.
When access to a data page is sought, comparisons are made: 1) between the high
order virtual address component of the data page and the high order virtual address
component read from the target associative memory entry; and 2) between the multi-digit
validity count read from the target associative memory entry and the multi-digit
current validity count in the target counter. If there is a full match, the real
page address of the requested page is read from the target associative memory entry.
If there is not a match, the page table is consulted to obtain the real address
of the requested page, and the target associative memory is updated accordingly.
