A system that includes a first circuit configured generate a first set of encoded
signals in response to a first clock signal and a second circuit configured to
generate a second set of encoded signals in response to the first clock signal
is provided. The system also includes a third circuit configured to generate a
first pulse signal and a second pulse signal in response to the first set of encoded
signals and the second set of encoded signals, and a fourth circuit configured
to generate a second clock signal in response to the first pulse signal and the
second pulse signal.
