A shift register includes a plurality of pulse generation portions for generating
a series of pulse signals in response to a level change of inputted clock signals,
and a plurality of shift pulse generation units. The plurality of shift pulse generation
units has a predetermined shift pulse generation unit, with the predetermined shift
pulse generation unit having a status signal generation circuit for outputting
a first status signal to common wiring to which both of an earlier shift pulse
generation unit and a later shift pulse generation unit are connected, and a clock
supply circuit for supplying a clock signal to the pulse generation portion which
belongs to the predetermined shift pulse generation unit. In addition, there is
a first period in which the clock supply circuit supplies the clock signal to the
pulse generation portion which belongs to the predetermined shift pulse generation
unit and a second period in which the clock signal is not supplied. During the
first period in which the clock signal is supplied, a status signal is inputted
from the earlier shift pulse generation unit, and a status signal is not inputted
from the later shift pulse generation unit.
