A memory device includes a memory cell configured to be coupled to complementary
first and second bit lines and a differential amplifier having first and second
input terminals and operative to amplify a voltage between the first and second
input terminals to produce an output signal. First and second voltage-dependent
capacitors are coupled to respective ones of the first and second input terminals,
and first and second isolation switches are operative to couple and decouple the
first and second bit lines to and from respective ones of the first and second
voltage-dependent capacitors. The first and second isolation switches may include
respective first and second isolation transistors (e.g., NMOS transistors), and
the first and second voltage-dependent capacitors may include respective MOS capacitors.
