Pattern generator for semiconductor test system

   
   

A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion request signals for inverting the read/write data for specified memory cells for a memory device under test having different total numbers of memory cells between X (row) and Y (column) directions. The locations of specified memory cells are on a diagonal line on an array of memory cells in the memory device under test or on a reverse diagonal line which is perpendicular to the diagonal line.

 
Web www.patentalert.com

< High speed interface device for reducing power consumption, circuit area and transmitting/receiving a 4 bit data in one clock period

< Apparatus for high data rate synchronous interface using a delay locked loop to synchronize a clock signal and a method thereof

> Rewriting system for rewriting a memory on a vehicle controller

> System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits

~ 00193