In one embodiment, a plurality of contact holes are formed using an self-aligned
contact (SAC) process to expose active regions. When storage node contact or BC
pads are formed in the contact holes, a conductive layer is partially filled in
the contact holes to expose the sidewall of an interlayer insulating layer pattern
over the BC pads. The exposed sidewall of the interlayer insulating layer pattern
is covered with an etch stop spacer. Also, the top surface of the interlayer insulating
layer pattern is covered with an etch stop layer. Then, a plurality of bit line
contact or BC plugs are formed to contact the tops of the BC pads. A protruded
region, which extends in one direction, is preferably formed on the sidewall of
the contact plug.
