Method and apparatus for aligning semiconductor chips using an actively driven vernier

   
   

One embodiment of the present invention provides a system that facilitates measuring an alignment between a first semiconductor die and a second semiconductor die. The system provides a plurality of conductive elements on the first semiconductor die and a plurality of conductive elements on the second semiconductor die. The plurality of conductive elements on the second semiconductor die have a different spacing than the plurality of conductive elements on the first semiconductor die, so that when the plurality of conductive elements on the first semiconductor die overlap the plurality of conductive elements on the second semiconductor die, a vernier alignment structure is created between them. The system also provides a charging mechanism configured to selectively charge each of the plurality of conductive elements on the first semiconductor die, wherein charging a conductive element on the first semiconductor die induces a charge in one or more conductive elements on the second semiconductor die. An amplification mechanism then amplifies the signals induced in the conductive elements on the second semiconductor die. These signals can be analyzed to determine the alignment between the first semiconductor die and the second semiconductor die.

 
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