A test code is input to a test mode control circuit so that the test mode control
circuit creates the test decode signal. The test decode signal is converted into
serial data with a parallelserial converting circuit in synchronization with
a base clock. The serial data is input to a serialparallel converting circuit
located in the vicinity of the test code latch circuit dispersed on the semiconductor
chip via one very long serial data line extending from end to end of the semiconductor chip.
