A structure of and a method for making an isolated NMOS transistor using standard
BiCMOS processing steps and techniques. No additional masks and processing steps
are needed for the isolated NMOS device relative to the standard process flow.
A P-type substrate with an overlaying buried N-type layer overlaid with a buried
p-type layer below a P-well is shown. An N-type region surrounds and isolates the
P-well from other devices on the same wafer. N+ regions are formed in the p-well
for the source and drain connections and poly or other such electrical conductors
are formed on the gate, drain and source structures to make the NMOS device operational.
Parasitic bipolar transistors are managed by the circuit design, current paths
and biasing to ensure the parasitic bipolar transistors do not turn on.
