Ferroelectric memory device

   
   

A high-speed accessible ferroelectric memory device includes ferroelectric capacitors (memory cells) at respective intersecting points of a plurality of word lines and a plurality of bit lines. A voltage supply line for a selected word line and a voltage supply line for an unselected word line are connected with a word line driver section which drives the word lines. A voltage supply line for a selected bit line and a voltage supply line for an unselected bit line are connected with a bit line driver section which drives the bit lines. A voltage select circuit which selects the voltages of the supply lines fixes the potential of one of the voltage supply line for the unselected word line and the voltage supply line for the unselected bit line in both cases of applying a positive and negative select voltages to a selected memory cell (read period and write period).

 
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