A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n-1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n-1 lower order bits of the branch target address to form the complete branch target address.