A semiconductor wafer is produced with an outer contact layer applied to the entire surface of an insulating layer and a rewiring layer embedded therein. At the same time, fuses are short-circuited. After the outer contact layer has been patterned and a passivation layer has been applied, outer contacts and short-circuit lines are uncovered. Outer contacts are introduced into passage openings in the passivation layer. The semiconductor structures are tested and predetermined short-circuit lines are interrupted. Then, the semiconductor wafer is diced into semiconductor chips.

 
Web www.patentalert.com

< Multi-chip package and manufacturing method thereof

< Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them

> Semiconductor device having multilevel copper wiring layers and its manufacture method

> Stress-relief layer for semiconductor applications

~ 00217