The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.