An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond the gate section on opposite sides thereof. A dielectric layer has an upper surface spaced above the upper ends of the side walls. Contact openings are created through the dielectric layer, so as to expose surface portions on the source and drain regions. Conductive contacts are formed in the contact openings. The portions of the side walls which project above the gate section permit misalignment of the contact openings, without exposing any portion of the gate electrode during formation of either contact opening.