A circuit for generating video synchronization timing signals includes a negative
peak detector (FIG. 5) for following variations of a composite video signal
(FIG. 1), rather than clamping the most negative voltage of the composite
video signal. The negative peak detector provides a voltage level VTIP
representative of the voltage at the synchronization tip of the composite video
signal. A sample and hold circuit (700, 702, 704) is used to add an offset
VSLICE to VTIP, VSLICE being a voltage level of
the breezeway, color burst, or back porch segments of the composite video signal,
or a combination of these segments. The sample and hold circuit generates a signal
VREF, and is connected by a resistor divider (708,710) to the
negative peak detector to form the signal VTIP+VSLICE provided
to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP
is compared in comparator (606) with the composite video signal to
provide an overall circuit output. Buffering is provided at the input of the negative
peak detector by amplifier (600) to reduce any DC offset from the diode
of the negative peak detector. To prevent amplifier DC offset error voltages from
affecting the perceived VSLICE level, an amplifier (800) can
be connected in a first position TTIP as part of a negative peak detector
to store VTIP on a capacitor, in a second position TH as
part of a sample and hold circuit to store VREF on a capacitor, and
in a third position TCOMP to compare VSLICE+VTIP measured
from the capacitors with the composite video signal to generate the overall circuit output.
