A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

 
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< Semiconductor apparatus having a built-in-electric coil and a method of making the semiconductor apparatus

< Prefabricated semiconductor chip carrier

> Semiconductor packaging device

> Interconnect substrate and method of manufacture thereof, electronic component and method of manufacturing thereof, circuit board and electronic instrument

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