A low-resistance silicon baseplate (11) has formed thereon a buffer layer 12 in the form of an alternating lamination of AlN sublayers (12a) and GaN sublayers (12b). On this buffer layer there are formed an n-type semiconductor region (13) of gallium nitride, an active layer (14) of gallium indium nitride, and a p-type semiconductor region (15) of gallium nitride, in that order. An anode (17) is formed on the p-type semiconductor region (15), and a cathode (18) on the baseplate (11).