An integrated circuit (7A) for multitasking support for processing unit
(1A) holds control variables for each task (or activity) to run on its associated
processor (1A) and identifies the next task that should run. The circuit
(7A) employs level-driven, clock free ripple logic and is configured as
a two dimensional array of "tiles", each tile being composed of simple logic gates
and performing a dedicated function. The circuit has particular application to
asynchronous multiple processor networks.