A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

 
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< Semiconductor package with crossing conductor assembly and method of manufacture

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> Stacked chip electronic package having laminate carrier and method of making same

> Multi-bit ROM cell, for storing one of n4 possible states and having bi-directional read, an array of such cells, and a method for making the array
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