Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of the delays caused by the TDM channel. The TDM channel is modeled with its equivalent delays. Thus, a transformation tool is allowed to take into account the original constraints and time budgeting of the sending subsystem and the receiving subsystem. The problem of asynchronous clock domains is eliminated; and, simulation time of the multiplexed circuit is also improved. In some embodiments of the present invention, multiple TDM slots are assigned to a particular signal to reduce the equivalent connection delay caused by the TDM channel for the particular signal. In some embodiments of the present invention, timing simulation is performed using the equivalent delays to avoid the simulation of the TDM hardware; and, the simulation time step does not have to be reduced due to asynchronous clock, resulting in reduced simulation time.