A high-speed memory system is disclosed in which a single command effects control
over either a single memory device or a plurality of memory devices depending on
a present mode of operation. Such control may effect data transfer between the
one or more memory devices and a memory controller, as well as operating state
transitions or power mode transitions for the memory devices. Similarly, various
configurations of relatively low bandwidth memory devices respond as a selectively
controllable group to transmit or receive high bandwidth data.