A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.

 
Web www.patentalert.com

< Rod target for arc evaporation source, manufacturing method therefor, and arc deposition device

< Nonlinear target recognition

> Method for increasing fracture penetration into target formation

> Automated system for isolating and amplifying a target nucleic acid sequence

~ 00259