The vector unit 21 outputs a first flash address to the flash address array 24. The vector unit 31 outputs a second flash address to the flash address array 34. In the master unit 2, the flash address array 24 compares an address registered in a cache with the first flash address. In the slave unit 3, the flash address array 34 compares the address registered in the cache with the second flash address. When said first flash address coincides with said address registered in said cache, the flash address array 24 sends a first coincidence address to the address array 25. When said second flash address coincides with said address registered in said cache, the flash address array 34 sends a second coincidence address to the address array 25. A corresponding address of the address array 25 is flashed based on the first address sent from the flash address array 24 and based on the second address sent from the flash address 34. The cache control circuit 23 receives an END signal from the master unit 2 and an END signal from the slave unit 3. Thus, the flash process ends.