A semiconductor memory device includes a first write wiring which has first to third running portions, first and second oblique running portions, the first and second running portions running in a first direction, the third running portion running on substantially a same line as the first running portion, the first and second oblique running portions running in first and second oblique directions, a second write wiring which has fourth to sixth running portions, third and fourth oblique running portions, the fourth and fifth running portions running in a second direction, the sixth running portion running on substantially a same line as the fourth running portion, the third and fourth oblique running portions running in third and fourth oblique directions, and a memory element which is at least partially sandwiched between the first and third oblique running portions.