The objective is to provide a data transfer control device and electronic equipment that make it possible to switch the frequency of a generated clock dynamically, without causing any operating errors. The data transfer control device includes a clock generation circuit which generates clocks CLKH and CLKF and a clock control circuit which generates a system clock SYCLK based on CLKH and CLKF. The autonomous operation of a PLL60M that generates CLKF is enabled before the autonomous operation of a PLL480M that generates CLKH is disabled, and the generation source of SYCLK is switched from CLKH to CLKF after the autonomous operation of the PLL60M has stabilized. On condition that CLKH becomes "0", SYCLK is set to "0" for a given period only; and on condition that CLKF becomes "0", SYCLK is generated based on CLKF. When the mode switches from HS mode FS mode under USB 2.0, the operation of the PLL480M is disabled, reducing the power consumption.