The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.