An integrated circuit chip module assembly (10) is disclosed that electrically interconnects the bond pads of the various integrated circuit chips (20) in the module to circuitry (42) on a thin film multilayer membrane (22). The module assembly includes a heat sink (16) with the back surfaces of the chips (20) in thermal engagement therewith. Contacts (40) of the bond pads of the chips (20) are in electrical engagement with the circuitry (42) on the membrane (22) and are accurately positioned by means of nests (28) formed on the surface of the membrane (22). A contact pressure equalizer (12) engages only selected areas (98) of the membrane (22) opposite the contacts (40) of the chips (20) to urge the contact surfaces (44) on the membrane (22) into electrical engagement with raised contacts (40). The contact pressure equalizer (12) includes a relatively large pressure plate (70) having a layer (74) of relatively soft rubber thereon. A plurality of rigid plates (78) are positioned on the soft rubber layer (74) so that each plate is opposite a respective chip (20). A narrow strip (88) of relatively hard rubber is positioned on each of the rigid plates (78) so that the hard rubber strips engage only the selected areas (98) of the membrane (22). The heat sink (16) and the pressure plate (70) are then bolted together with the chips (20), the hard rubber strips (88), the rigid plates (78), and the soft rubber layer (74) sandwiched in between.