Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardware using a free-running clock, for example to speed up test time and to generate information related to operational speed. A simulation of the hardware is used, where single-step clocking out the test results facilitates verification of the hardware test results with simulation test results.