A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to operate in the fast clock domain in conjunction with hardware that performs certain device operations that is clocked by a slow clock that is always on to operate in a slow clock domain. Writing data from the processor to the hardware involves determining if a bit is to be written to a register of the slow clock domain in synchrony with a transition of the slow clock, stopping the fast clock to pause operation of the processor, writing the bit to the register of the slow clock domain upon a succeeding slow clock transition, and starting the fast clock to resume operation of the processor.