A memory module contains a plurality of memory devices and receives control signals over a memory bus for accessing the memory devices. An adaptive buffering mechanism includes unregistered logic to electrically isolate the received control signals from one or more control drive signals. Register logic substantially synchronizes the control drive signals to a system clock to produce clocked control drive signals. A mode selection mechanism selectively outputs either the control drive signals or the clocked control drive signals to access the memory devices in accordance with a mode selection signal.