An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer. The upper metallization traces are configured to electrically connect with the first plurality of pairs of conductive vias and maintain the dummy conductive trace and the pair of dummy conductive vias in an unused and electrically floating condition.