A transistor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.

 
Web www.patentalert.com

< Optical information recording medium manfacturing method therefor, manufacturing apparatus therefor, and optical information recording and reproducing apparatus

< Capacitor element, manufacturing method therefor, semiconductor device substrate, and semiconductor device

> Lateral power MOSFET for high switching speeds

> Method of forming metal/high-k gate stacks with high mobility

~ 00292