Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.