A digital synthesizer includes a digital radio frequency memory (DRFM) for storing phase values and corresponding digital signals. The digital synthesizer includes a digital processing circuit receiving input from the DRFM, the circuit including tapped delay lines and a summer summing the output of the tapped delay lines. The digital synthesizer includes a signal modulator independently synthesizing within each tapped delay line a frequency modulated and gain scaled signal, wherein input to the tapped delay lines are phase values from the DRFM.