A multiple input look up table (LUT) structure adapted for carry-logic implementation, wherein each input is received in true and compliment levels, comprising: an output of an intermediate stage within the LUT structure; and a LUT value input of a stage next to said intermediate stage; and a multiplexer (MUX) structure coupled between the output and the LUT value input, wherein the MUX structure further comprises: a plurality of secondary inputs, including a carry-in logic signal; and a configuration circuit to couple one of the output or a said secondary input to said LUT value input.