In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also configured to monitor for a plurality of conditions for each thread, wherein each of the plurality of conditions defined to inhibit the thread from being fetched. The fetch generator circuit is configured to speculatively generate a first fetch request for a first thread of the plurality of threads if each thread is inhibited from fetching and the first thread is inhibited from fetching only due to a first predetermined condition of the plurality of conditions. In one particular implementation, the first predetermined condition is a lack of room in a corresponding one of a plurality of instruction buffers.