One embodiment of the present invention provides a system that migrates a layout of a cell which is used in integrated circuit design. During operation, the system receives a layout for the cell, wherein one or more layers of the cell contain tracks for metal wires. The system then determines how many tracks are to be inserted into the cell. Next, the system inserts one or more extra tracks between the tracks in the cell. The system subsequently adjusts the widths of the inserted tracks and the original tracks to increase the total number of tracks within the cell while maintaining the metal wires at the center of their original tracks.

 
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> Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules

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