The present invention relates to the field of computer hardware locic
circuits, and in particular to a method for verifying the proper
operation of a digital logic circuit, and in particular to symbolic
simulation of a gate-level netlist corresponding to said hardware logic
circuit. In order to add a useful alternative in the field of functional,
exhaustive simulation and of symbolic simulation, it is proposed to
perform the steps of: a) analyzing symbolic expressions visible at
predetermined locations within said logic; b) determining, which nets in
the netlist carry complex symbolic expressions, which comprise more than
one symbol; c) replacing said complex expressions with a "crunshed
color", for cutting off said complex symbolic expression from further
propagation through the netlist; d) continuing said symbolic simulation
including said crunched color information on predetermined nets.