A method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area is used in a process for manufacturing semiconductor integrated non-volatile memory devices, wherein an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the array and circuitry areas. A thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry. This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.