A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.