A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of grid areas, arranging the logic cells in each grid area, determining whether the decoupling capacitance is sufficient in each grid area for the logic cells in that grid area, and performing a supplementing process of the decoupling capacitance based on whether the decoupling capacitance is sufficient.

 
Web www.patentalert.com

> System and method for manipulating an integrated circuit layout

~ 00350