A control circuit for a DC-DC converter that prevents erroneous operations during high ON-duty operation. In response to an H-level pulse signal, a random delay circuit generates a delayed pulse signal that rises to an H level within one cycle of the pulse signal. The random delay circuit randomly changes the delay time of the delayed pulse signal. Even if noise causes the timing at which a current comparison signal rises to an H level to be delayed to later than the timing at which an H-level pulse signal is provided to the set terminal of an FF circuit, the FF circuit receives at its reset terminal an H-level delayed pulse signal that is provided prior to the H-level pulse signal. The FF circuit then inactivates the output transistor.