FIFO memory devices include a multi-port cache memory device configured to
generate a data word along with a plurality of diagnostic bits. These
diagnostics bits encode an error correction status of the data word and a
path traversal status of the data word through the FIFO memory device. In
particular, the diagnostic bits identify all cases of whether the data
word includes a corrected or uncorrected error, is without error or is
unchecked for errors because the data word did not pass through error
detection and correction circuitry within the FIFO memory device.