The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b connected to each other via the bottom surface side of the P-type Si substrate 109, and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103a, 103b. The semiconductor device also has NMOS transistors 107a, 107b provided on the P-type wells 103a, 103b, and PMOS transistors 105a, 105b, 105c provided on the N-type well 101. The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.

 
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> Ultra-shallow metal oxide surface channel MOS transistor

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