An efficient and automated algorithm for placing power gating switches within a voltage island of an integrated circuit, which ensures compliance with defined electrical specifications. A power gating switch is placed in every legal location on the integrated circuit and the minimum number of power gating switches is calculated based on current requirements of the voltage island. Each power gating switch is modeled as an ideal resistor whose value is obtained from the slope of the I-V curve of the switch when operating in the linear region. The power distribution networks of the integrated circuit and the voltage island are extracted and modeled as a resistive network. Circuit macros placed within the voltage island are modeled as current sources. The extracted linear network is then simulated using a DC stimulus to obtain expected voltage drops across the voltage island as well as the currents in all branches of the voltage island power grid and through each power gating switch. The process iterates until a placement of a minimum number of power gating switches is found that guarantees compliance with the electrical specifications.