A semiconductor memory device has first and second sense nodes which are
provided corresponding to first and second bit lines, and a sense
amplifier which is connected to the first and second sense nodes and
senses data read out from a memory cell, wherein the sense amplifier
includes an initial sense circuit which increases a potential difference
between the first and second sense nodes in a first period after
beginning sense operation, and a latch circuit which increases and holds
the potential difference between the first and second sense nodes in a
second period after the first period, wherein the initial sense circuit
includes first and second transistors of first conductive type, third and
fourth transistors of first conductive type, and fifth and sixth
transistors of first conductive type, wherein the latch circuit includes
seventh and eighth transistors of first conductive type, and ninth and
tenth transistors of second conductive type.