A storage control device of bank structure is provided which comprises a CPU 1 and a storage 2 connected to CPU 1. Storage 2 detects and temporarily holds one of the bank addresses 0DF00h-7DF07h of the bank memories 9 to be read out next by CPU 1 when one of the bank memories 9 is read out by CPU 1 so that storage 2 supplies the held bank address 0DF00h-7DF07h to a memory control device 3 which thereby is switched to a next bank memory when CPU 1 produces a next retrieval signal. Accordingly, CPU 1 of small capacity reads information from storage of larger capacity to operate a controlled system connected to CPU 1 of the storage control device.

 
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> Method and system for concurrent error identification in resource scheduling

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