A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.

 
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> Wafer-leveled chip packaging structure and method thereof

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