The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed. Sandwich layer portions extending from the Cu component are removed from the substrate, thereby forming an exposed sandwich layer edge between the surface of the Cu component and the substrate. A Cu diffusion barrier layer is deposited on the Cu component and on the exposed edge of the sandwich layer, resulting in a Cu barrier layer encapsulated component. The encapsulated component is encased in a dielectric layer. Similarly, Cu components of the present invention are fabricated by means of selective electroless Cu deposition in a sacrificial layer cavity having a metal layer that is formed by selective electroless deposition of a metal on a sensitizer layer. Examples of Cu components and encapsulated Cu components of the present invention include vertical interconnects and inverted damascene structures.