An address converter of a semiconductor device comprises a clock
generating portion for generating at least one clock signal when a power
voltage is applied; a control signal setting means for setting a control
signal during a mode setting operation; a polarity selecting signal
generating portion for generating at least one polarity selecting signal
in response to the at least one clock signal and the control signal; and
an address converting portion for converting at least one bit of an
address applied from an external portion to output a converted address in
response to the at least one polarity selecting signal.